TopSPICE is still the price/performance leader in true analog/digital/behavioral mixed-mode simulation for the PC. It offers the most advanced simulator in its price range, compatibility, and a quick and easy to use integrated design environment from schematic capture to graphical waveform analysis.
With TopSPICE you have the choice to design from schematic drawings or text netlist (SPICE) files, or switch between them. All design and simulation functions are available from either the schematic or netlist editor front-ends.
TopSPICE includes a native full-featured mixed-mode mixed-signal circuit simulator capable of simulating circuits containing any arbitrary combination of analog devices, digital functions and high-level behavioral blocks. With TopSPICE you can verify and optimize your design from the system to the transistor level. By using the built-in logic simulator to simulate the digital sections of your circuit instead of analog equivalents, mixed-mode simulation times can be reduced by orders of magnitude.
Native mixed-mode mixed-signal simulation.
Industry compatible SPICE simulator works with most PSpicetm and HSPICEtm netlists, and vendor SPICE model libraries.
Built-in event-driven logic simulator.
32-bit simulator supports large circuit sizes (up to available system resources).
Built-in device models: diode, BJT, MOSFET (levels 1, 2, 3, 7, 8, 44, 49, 53, 55), JFET, GaAs FET (levels 1, 2, 3, 6), MESFET, nonlinear magnetic core, ferroelectric capacitor, switch, lossy transmission line and digital primitives.
Extensive model libraries of analog and digital components.
HSPICEtm format model library support.
Analog behavioral modeling.
Analyses: bias point, DC sweep, transient, AC sweep, noise, distortion, sensitivity, tranfer function, Fourier, temperature, Monte Carlo, parametric stepping, "alter" circuit.
Interactive graphical post-processor with "auto plot".
Waveform expression plots.
Powerful waveform, performance and statistical analysis functions.
All design and simulation functions are available from either the schematic or netlist editor front-ends.
DEMO VERSION LIMITATIONS
Schematic Editor limits: maximum number of schematic parts about 36; multiple sheet schematics not supported; symbol utilities or saving subcircuits as models not supported.
Simulator limits: number of nodes 64; number of top level transistors and subcircuits 10; number of subcircuit transistors 15; total number of top level components 30; number of subcircuit definitions (macromodels) 5; maximum data memory usage 1 MBytes.
Post-processor plot limits: number of traces 16; number of points per trace 16K.
